1. Field of the Invention
The present invention relates to a semiconductor device having a trench isolation structure used in a CMOS device and the like having multiple power supply voltages.
2. Description of the Related Art
In a semiconductor device having a CMOS device which uses multiple power supply voltages, it is important to improve a degree of integration of a low voltage section forming an internal circuit such as a logic circuit, and at the same time, to prevent formation of parasitic transistors in the device isolation region to secure latch-up resistance of a high voltage section used for an input/output circuit or the like.
In recent years, the device isolation is carried out by trench isolation which is more suitable for higher integration than LOCOS isolation in many cases. In LOCOS, however, a heavily doped impurity region for preventing parasitic channel, that is, a so-called channel stopper region or a field dope region can be easily formed to prevent inversion of a semiconductor substrate, and thus, the device isolation characteristic for a high voltage circuit is excellent. On the other hand, a semiconductor device in which trench isolation is used for device isolation has a problem in that, due to a potential of a interconnect which passes above the trench isolation region, a parasitic channel can be formed easily because a parasitic inversion layer is formed on the surface of a semiconductor substrate in the lower part of the trench isolation region, leading to a problem of, in particular, forming a high voltage power supply circuit section.
The formation of an inversion layer and a parasitic channel, and latch-up caused by the formation of the inversion layer and the parasitic channel, are described with reference to FIG. 3.
FIG. 3 is a schematic cross sectional view illustrating a part of a high voltage circuit section of a conventional semiconductor device.
A p-well region 201 of a p-type lightly doped impurity region as a first well region and an n-well region 202 of an n-type lightly doped impurity region as a second well region are formed side by side on a p-type silicon substrate 101 as a semiconductor substrate of a first conductivity type. An n-type heavily doped impurity region 501 which is a source and/or a drain region of an n-type MOS transistor, for example, is formed on a surface of the p-well region 201, while a p-type heavily doped impurity region 502 which is a source and/or a drain region of a p-type MOS transistor, for example, is formed on a surface of the n-well region 202. A trench isolation region 301 for device isolation is formed between the n-type heavily doped impurity region 501 and the p-type heavily doped impurity region 502. A interconnect 901 formed of aluminum or the like for electrically connecting the elements is disposed thereabove via a first insulating film 601 which is a silicon oxide film or the like.
In a high voltage circuit in which a power supply voltage of 30 V, for example, is used, a potential of 30 V is sometimes applied to the interconnect 901. Since the potential of the p-well region 201 is fixed at the ground level (0 V), an n-type inversion layer 911 is easily formed under the trench isolation region 301 in the p-well region 201. Then, a parasitic transistor formed of the n-type heavily doped impurity region 501, the n-type inversion layer 911, and the n-well region 202 is brought into conduction to permit on-state current. Due to a rise in the potential of the n-well region 202 caused by the on-state current, a vertical parasitic PNP transistor formed of the p-type heavily doped impurity region 502, the n-well region 202, and the p-type silicon substrate 101 is turned on. This causes a potential drop of the p-well region 201, and a so-called latch-up phenomenon occurs.
However, in order to secure enough latch-up resistance for a high voltage circuit section, it is necessary to increase the depth of a well to suppress parasitic bipolar action, and, in order to reduce leakage current between an NMOS transistor and a PMOS transistor and to secure high voltage withstand characteristics, it is necessary to make the width of a trench isolation section larger. Therefore, there is a problem that, when the low voltage circuit section uses the same trench isolation structure as the trench isolation structure of the high voltage circuit section, the degree of integration of a device in the low voltage section which is required to be higher reduces.
As measures for improvement thereof, a method of making the depth of a well of the high voltage circuit section larger than the depth of a well of the low voltage circuit section or a method of making the width of a trench isolation section of the high voltage circuit section larger than the width of a trench isolation section of the low voltage circuit section is proposed (see JP 2000-58673 A, for example).
As described above, however, in a semiconductor device with multiple power supply voltages whose elements are isolated by trench isolation, in order to secure enough latch-up resistance for a high voltage circuit section, it is necessary to increase the depth of a well to suppress parasitic bipolar action, and, in order to reduce leak current between an NMOS transistor and a PMOS transistor and to secure high voltage withstanding characteristics against inversion, it is necessary to make the width of a trench isolation section wider. Accordingly, there is a problem in that, when the low voltage circuit section uses the same trench isolation structure as the trench isolation structure of the high-voltage circuit section, the degree of integration of devices in the low voltage section reduces against the demand for high integration.
Though an improvement has been proposed in which the depth of a well of the high voltage circuit section is made larger than the depth of a well of the low voltage circuit section or the width of a trench isolation section of the high voltage circuit section is made larger than the width of a trench isolation section of the low voltage circuit section, there are problems in that the number of the manufacturing steps increases and that the increase in the width of a trench isolation section leads to increase in cost.